Conventional semiconductor integrated circuit devices of a double metal structure have been mass produced. One semiconductor integrated circuit (IC) device of this kind is provided with an interior operation area (active area), which is to be a circuit element portion, and a pad area formed on a surface of the semiconductor IC device.
The operation area is an area in which circuit elements such as a transistor, a diode and the like, and metal wiring layer (for example a metal wiring layer made of aluminum or the like) for connecting the circuits elements with each other are formed.
The pad area is an area in which electrodes (protruded electrodes) for connecting the semiconductor IC device with an external connecting terminal is formed, and with which input and output of a signal are performed. Note that a shape and a size of the protruded electrodes depend on pitches (intervals) to be formed. For example, for use in a liquid crystal driver, the protruded electrodes having a rectangular shape having a size of 40 μm×90 μm is so formed as to have pitches in a range of 50 μm to 80 μm around the semiconductor IC device.
Moreover, usually the protruded electrodes are formed not in the operation area, but around the operation area so that, for example, stress such as mechanical pressure or thermal stress will not be applied on the operation area via the protruded electrodes in connecting the protruded electrodes with the external terminals.
Recently, the miniaturization and weight reduction (improvement to be lighter, thinner, shorter, and smaller) of electronic apparatuses such as portable phones and portable information terminals urges electronic parts for those apparatuses to be packed more densely (to be improved in terms of density). This complicates a pattern of the metal wiring layer for connecting the circuit elements with each other in the semiconductor IC device, and produces a trend of use of multilevel interconnection structure in which a plurality of metal wiring layers are layered.
This also causes the semiconductor IC device to have a number of terminals for establishing the connection with external connecting terminals that may be in a range of up to 500 to 600 terminals. This causes the pad area to be larger, thereby giving the semiconductor IC device a larger size, going against the trend of miniaturization and weight reduction in portable phones, PDA (Personal Digital Assistants) and the like.
As an art to reducing the weight of the semiconductor integrated circuit device, an art called “area pad” is suggested, in which protruded electrodes are formed in an operation area of the semiconductor IC circuit device. An example of such semiconductor IC device is disclosed in Japanese Publication of Unexamined Patent Application, Tokukaihei, No. 11-8247 (published on Jan. 12, 1999). In the semiconductor IC device, a first wiring layer and interlayer film are provided on an active element, while a second wiring layer and a barrier metal are provided under protruded electrodes in this order. Further, the interlayer film and the barrier metal are bonded together via a cohesion film (insulating film). The cohesion film has a property to attain high cohesion with the barrier metal. Thus, the barrier metal and the interlayer film are highly cohered so that the barrier metal will be hardly peeled off from a layer located below the barrier metal, for example, even if an external force such as stress caused during bonding is applied thereon. In addition, for attaining electrical connection with the protruded electrodes, a barrier metal is also provided between the protruded electrodes and the second wiring layer.
Recently, a semiconductor IC device, which is produced by using the “area pad”, for liquid crystal display panels for example, is packaged (bonded) on a tape carrier (for example, a tape in which a pattern of a metal wiring is formed on an insulative film substrate. Such mounting method is called COF (Chip-ON-FPC (Flexible Printed Circuit)) method.
Referring to FIGS. 3(a) and 3(b), how the packaging is carried out in the COF method is explained below together with explanation on members used in the packaging. Note that FIG. 3(a) is a schematic cross-sectional view of a semiconductor IC device before connecting protruded electrodes with a metal wiring pattern by using the ILB method later described, while FIG. 3(b) is a schematic cross-sectional view of a semiconductor IC device after connecting protruded electrodes with a metal wiring pattern by using the ILB method.
As shown in FIG. 3(a), a semiconductor IC device 121 is provided with, on a surface thereof, a metal wiring layer (aluminum pad) 103, which functions as terminal electrodes for input and output. Further, the semiconductor IC device 121 is provided with protruded electrodes 107 below the metal wiring layer 103. Note that the protruded electrodes 107 are formed by plating gold (Au) on the metal wiring layer 103, and has a thickness of 10 μm–18 μm.
On the other hand, an insulative film substrate 122, on which the semiconductor IC device 121 is packaged, is provided with, on a surface thereof, a metal wiring pattern (lead frame) 123.
The insulative film substrate 122 is a member made mainly of a polyimide resin or polyester and having a belt-like shape. The insulative film substrate 122 is provided with feed holes at predetermined intervals on both edges thereof, so that the insulative film substrate 122 can be moved in its longitudinal direction.
The metal wiring pattern 123 is made of a conductive material such as copper (Cu) or the like, and tin (Sn), Au, or the like is plated on a surface of the metal wiring pattern 123. In addition, the metal wiring pattern 123 is provided with an inner lead, an outer lead, and an intermediate lead, and the like.
By using a bonding tool 124 (see FIG. 3(a)), the semiconductor IC device 121 is jointed (bonded) with the insulative film substrate 122. Specifically, as shown in FIG. 3(b), the protruded electrodes 107 and the metal wiring pattern 123 are joined by thermo compression in which the bonding tool 124 is used. Note that such a bonding method is generally known as the ILB (inner Lead Bonding).
After the ILB, even it is not illustrated here, the semiconductor IC device is sealed with a resin (resin encapsulation) by using an epoxy resin, a silicon resin or the like. In the resin encapsulation, the resin is applied around the semiconductor IC circuit by using a nozzle, and cured by heat application by the reflow method or the like. Thereafter, packaging section of the semiconductor IC device is stamped out of a tape carrier, and mounted, as individual semiconductor IC device (semiconductor package) on a liquid crystal display panel or the like.
However, in the semiconductor IC device 121 of the publication, the following problems may occur.
FIGS. 4(a) and 4(b) are respectively schematic cross-sectional views and plan view illustrating only main members of the semiconductor IC device 121. As shown in FIG. 4(a), the semiconductor IC device 121 is provided with, on a first wiring layer 101, an interlayer insulating film 102 for planarizing (leveling off, compensating) level-difference caused by the first wiring layer 101 (that is, level-difference caused by pitches Q of the first wiring layer 101). The interlayer insulating layer is made mainly of a soft material such as SOC (Spin-On-Glass).
Moreover, on the interlayer insulating film 102, a metal wiring layer (second wiring layer) 103 is provided. A protective film 104 is provided on the second wiring layer 103 so that the whole second wiring layer 103 except part thereof in which a window section 106 is provided is covered with the protective layer 104. Further, the second wiring layer 103 is electrically connected with the protruded electrodes 107 via the barrier metal 105 provided on the protective film 104 and the window section 106.
Here, in connecting the protruded electrodes 107 with a metal wiring pattern (external connecting terminal), that is, in bonding the protruded electrodes 107 with the external connecting terminal, there is a possibility that stress will be applied on the protruded electrodes 107 thereby making a crack C in the protective film 104 on the second wiring layer 103. Further, there is possibility that the crack C will be widened thereby allowing water to invade therein and cause corrosion, and finally causing such failure as electrical disconnection.
The crack C is caused because the interlayer insulating film 102 made of SOG, which is soft (has low hardness), is bent when stress is applied on the protruded electrodes 107, or when stress is applied on the second wiring layer 103. Especially, the warping is prominent when no first wiring layer 101 is provided.